Publications

Pattern based packet filtering using NetFPGA in DETER infrastructure

Abstract

The Cyber DEfense Technology Experimental Research (DETER) testbed is a networking testbed that allows researchers to perform security focused simulation and experiments in a controlled environment. In this paper, we describe the integration and the use of a hardware/software co-design host with the NetFPGA card, an open source field programmable gate array (FPGA) based network interface. Through our case study, we also demonstrate how schematic based module design can simplify development of NetFPGA modules. The case study module is a simplified network intrusion detection system which uses deep packet inspection. We deploy and exercise our system using the DETER testbed.

Date
2010
Authors
Andrew Goodney, Shailesh Narayan, Vivek Bhandwalkar, Young H Cho
Journal
1st Asia NetFPGA developers workshop. Daejeon, Korea