Abstract

This proposal addresses the grand challenge of reducing power consumption of digital electronic circuits leveraging off of a promising new automated design flow for asynchronous circuits. This novel flow actively manages data-flow within the circuit and is capable of disabling computational blocks that would otherwise perform unnecessary calculations and waste power. The proposed research is to develop mathematical software algorithms that will optimize the partitioning of the circuit into computational blocks to maximize the blocks that are disabled and thereby minimize power consumption.

Date

2011

Authors

Peter A Beerel

Journal

NSF Award Number 1116416. Directorate for Computer and Information Science and Engineering

Volume

11

Issue

1116416

Pages

16416