Abstract

Disclosed are a method of forming vertical field effect transistor (s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin (s). Vertical surfaces of the second and fourth layers of the fin (s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin (s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be pre cisely controlled.

Date

2019

Authors

R Xie, S Bentley, MG Sung, C Park, S Soss, H Zang, X Wu, Y Qi, AP Jacob, ...

Inventors

Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven Soss, Hui Zang, Xusheng Wu, Yi Qi, Ajey P Jacob, Murat K Akarvardar, Siva P Adusumilli, Jiehui SHU, Haigou Huang, John H Zhang

Patent_office

US

Patent_number

10217846

Application_number

15873156