Seminars and Events
Photonic ASICs for Machine Intelligence
Event Details
Note:
The time of this seminar has been updated to 9AM PST (12PM EST) to accommodate a scheduling conflict. The date remains Dec. 8th.
Abstract
The rapid growing demand for AI services in conjunction with a dramatic chip shortage along with technology leaps such as 5/6G networks, cybersecurity threats, and quantum algorithms have resurrected a R&D push for advanced information processing and computing capability. To address these challenges, unique opportunities exist, for example, given by algorithmic parallelism of digital-analog hybrid non-van Neuman accelerators. Especially photonic-electronic ASIC compute paradigms hold the promise to enable non-iterative O(1) runtime complexity, ps-short latency, and TOPS/W throughputs. This opens prospects for next-generation hardware both for AI cloud services but also for accelerating edge computing such as enabled by compact and efficient PIC-CMOS co-designs pushing the SWAP envelope. As both a professor and a co-founder of a deep-tech venture, in this seminar I will share my insights on fundamental complexity scaling and algorithm-hardware homomorphism on the one hand, and system-level synergies and co- design optimization strategies on the other. I will introduce a novel photonic RAM capable of zero-static power consumption suitable for edge applications and a photonic tensor core accelerator leveraging WDM parallelism. Beyond matrix-matrix multiplication acceleration, I will show how convolutions can be accelerated as simple dot-product multiplications in the Fourier domain and using display light technology enables 1000×1000 matrix convolutions at 100us latency, or about 10x faster than today’s GPUs.
Host: Mike Haney <[email protected]>
Zoom: https://usc.zoom.us/j/94686366870 (Meeting ID: 946 8636 6870)
Please join the zoom meeting using your @USC.EDU Zoom account if possible.