Event Details

October 2, 2026

Join Zoom Webinar

Host: Steve Crago
POC: Amy Kasmir

 

Next-generation semiconductor packaging and heterogeneous integration demand advanced metal interconnect technologies to achieve ultra-high 3D interconnect densities. However, such densely integrated 3D systems significantly increase heat flux and power density—reaching 500–1000 W/cm²—which leads to severe thermal challenges, including thermal crosstalk, localized hotspots, and thermo-mechanical stress. These effects pose serious risks to device reliability and performance. As a result, effective and energy-efficient thermal management strategies are essential for enabling future high-density 3D systems. In this presentation, I introduce an exterior-to-core thermal management framework for 3D semiconductor chips and packaging, focusing on thermal transport phenomena across multiple length scales, from device and interconnect levels to chip- and package-level architectures. I will also highlight our recent advances in direct on-chip, package-level microfluidic cooling using both single-phase and two-phase approaches, near-junction cooling techniques, and the integration of novel thermal packaging materials designed for enhanced heat spreading and extreme thermal isolation.

Speaker Bio

Dr. Tiwei Wei (Senior Member, IEEE) is an Assistant Professor in the Department of Mechanical and Aerospace Engineering at UCLA and Associate Director of the UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS). Before joining UCLA, he was an Assistant Professor at Purdue University (2022–2025) and conducted postdoctoral research at Stanford University’s NanoHeat Lab. He earned his Ph.D. in Applied Mechanics and Energy Conversion (TME) with additional training in 3D System Integration at imec and KU Leuven in Belgium. Dr. Wei’s research focuses on advanced semiconductor packaging manufacturing and thermal integration technologies. He is the recipient of the 2026 IEEE Electronics Packaging Society Exceptional Technical Achievement Award, 2025 ASME Electronic and Photonic Packaging Division (EPPD) Early Career Engineer Award, IEEE EPS 2025 Regional Contributions Award, the 2024 Intel Rising Star Faculty Award, and the 2020 imec Ph.D. Excellence Award. He also serves as an Associate Editor for Microelectronics Reliability, IEEE T-CPMT, and ASME JEP, and has held key leadership roles in the IEEE EPS community, including General Chair of the 2024 IEEE EPS REPP (Reliability for Electronics and Photonics Packaging) symposium, Chair for IEEE EPS Technical Committee on Reliability and Assistant Chair for IEEE ECTC Interconnections Committee.