Abstract

The objective of this document (internal to ISI/NPS/Princeton) is to hash out details and design issues that may arise while integrating Secret Protected (SP)[rlee05] with the SCHW and the SecureCore architecture. This document describes the use of cryptographic hardware like SP and Trusted Platform Module (TPM)[tcgp05] within the context of the SecureCore project to provide cryptographic services. We start with describing the assumptions about the architecture, hardware, software and usage of the SecureCore device. We then describe the hardware requirements for virtualization of SP and how the virtualized SP is integrated into and used in the SecureCore architecture.

Date

January 1, 1970

Authors

Ganesha Bhaskara, Timothy E Levin, Thuy D Nguyen, Terry V Benzel, Cynthia E Irvine, Paul C Clark

Publisher

Technical Report NPS-CS-06-012, Naval Postgraduate School, Monterey, California