Abstract

This paper presents a novel multi-phase clocking methodology targeting multi-threaded gate-level pipelined sequential circuits. Gate-level-pipelined circuits, such as present in superconductive digital electronics, require many path balancing registers to enable proper multi-threaded computation. The paper introduces a novel integer linear programming (ILP) algorithm to minimize the number of required registers given the number of available clock phases and a corresponding number of processing threads. We evaluated our approach using eight SFQ benchmark circuits through path balancing, clock tree synthesis (CTS), and place-and-route (PnR). Compared with fully-balanced approaches, which require a very large number of threads to achieve peak throughput, the proposed method reduces the number of path-balancing registers by 55.5% with two clock phases and up to 95.5 % with ten clock phases. The …

Date

July 4, 2022

Authors

Xi Li, Min Pan, Tong Liu, Peter A Beerel

Conference

2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Pages

62-67

Publisher

IEEE