Abstract

Background
The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.
Aim
We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).
Approach
Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product.
Results
The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter …

Date

January 1, 2024

Authors

Jaime Bravo, Philippe Morey-Chaisemartin, Eric Beisser, Frederic Brault, Joshua Zusman, Jimmy Lefevre, Lifu Chang

Journal

Journal of Micro/Nanopatterning, Materials, and Metrology

Volume

23

Issue

1

Pages

011003-011003

Publisher

Society of Photo-Optical Instrumentation Engineers