Abstract

The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging. Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs. A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to …

Date

2023

Authors

Jaime Bravo, Philippe Morey-Chaisemartin, Lifu Chang, Eric Beisser, Frederic Brault, Joshua Zusman

Conference

DTCO and Computational Patterning II

Volume

12495

Pages

225-233

Publisher

SPIE