Abstract

Semiconductor foundries at 65nm, 45nm, and more advanced technologies have witnessed high-yield mass production to be intimately correlated to the practice of adaptive DFM (Design for Manufacturability). With device performance variance easily exceeding 50% for 65nm and below, adaptive actions by designers, such as modifying layouts to relieve potential DFM risks, is found to be a very efficient approach to high yield manufacturing. Rigorous MEEF estimation based methods have been proposed to achieve adaptive DFM by predicting mask writing variations at early stages (cell/block levels) of designs. In a recent study, we discovered that by adding MEEF check in simulation contour based OPC verification flow, and by comparing MEEF changes of pre and post OPC hotspots, it is possible to separate OPC issues from design issues, in particular, for hotspot patterns with tight spaces with little room for any …

Date

April 2, 2010

Authors

Li-Fu Chang, Chang-Il Choi, Guojie Cheng, Abhishek Vikram, Gary Zhang, Bo Su

Conference

Design for Manufacturability through Design-Process Integration IV

Volume

7641

Pages

299-306

Publisher

SPIE