Abstract

With process technologies advancing to 65nm, 45nm, and below, device timing uncertainty due to lithography and other process variations has easily exceeded 50% and is still growing. In this paper, we present the development of a variability methodology, its correlation with silicon and application to cell and full-chip design verification and optimization. We describe both a methodology for variability analysis of standard cells and a full-chip screening methodology to identify potential chip variability excursions. This methodology relies on model-based analysis and integrates with our existing design-to-manufacturing flow. Based on silicon measurement data of one of our 65nm cell libraries, this methodology has achieved significant improvement in accuracy of estimating timing variations compared to a traditional rule-based method.

Date

April 2, 2010

Authors

Li-Fu Chang, Julia Fu, Josh Yang, Elain Zou, Philippe Hurat, Nishath Verghese, Hua Ding

Conference

Design for Manufacturability through Design-Process Integration IV

Volume

7641

Pages

120-127

Publisher

SPIE