Abstract

Disclosed are embodiments of an integrated circuit structure (eg, a processing chip), which includes an array of inte grated pixel and memory cells configured for deep in-sensor, in-memory computing (eg, of neural networks). Each cell incorporates a memory structure (eg, DRAM structure or a ROM structure) with a storage node, which stores a first data value (eg, a binary weight value), and a sensor connected to a sense node, which outputs a second data value (eg, an analog input value). Each cell is selectively operable in a functional computing mode during which the voltage level on a bit line is adjusted as a function of both the first data value and the second data value. Each cell is further selec tively operable in a storage node read mode. Furthermore, depending upon the type of memory structure (eg, a DRAM structure), each cell is selectively operable in a storage node write mode. 20 Claims, 13 Drawing …

Date

2022

Authors

A Jaiswal, AP Jacob

Inventors

Akhilesh Jaiswal, Ajey Poovannummoottil Jacob

Patent_office

US

Patent_number

11468146

Application_number

16705434