Abstract

The present disclosure relates to a structure including a differential memory array circuit which is configured to perform a binary convolution of two input word operands by accumulating a summation of currents through a plurality of bits which are each arranged between a wordline and a sourceline in a horizontal direction and bitlines in a vertical direction.

Date

2021

Authors

A Agrawal, AP Jacob

Inventors

Amogh Agrawal, Ajey Poovannummoottil Jacob

Patent_office

US

Patent_number

10997498

Application_number

16366187