Abstract

(58) Integrated circuits, memory arrays and methods for operat ing integrated circuit devices are provided. In an embodi ment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the inte grated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

Date

2019

Authors

BC Paul, A Jaiswal, AP Jacob, W Taylor, DPC Shum

Inventors

Bipul C Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, William Taylor, Danny Pak-Chum Shum

Patent_office

US

Patent_number

10510392

Application_number

16047882