Abstract

A method, apparatus, and manufacturing system are dis closed herein for a vertical field effect transistor (VFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, ie, the vFET may be formed in a gate-first or a gate-last process.

Date

2019

Authors

AP Jacob, XA Tran, H Zang, B Haran, S Kalaga

Inventors

Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga

Patent_office

US

Patent_number

10461173

Application_number

15990186