Abstract

(57) ABSTRACT A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

Date

2017

Authors

MK Akarvardar, AP Jacob

Inventors

Murat K Akarvardar, Ajey P Jacob

Patent_office

US

Patent_number

9842897

Application_number

15176073