Abstract

(57) ABSTRACT A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include form ing first trenches in a Si, Ge, III-V, or Si, Ge-substrate; forming a conformal SiN, SiO C „N, layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or Si, Gel-x substrate; removing exposed portions of the Si, Ge, III-V, or Si, Ge, substrate, forming second trenches; forming III-V, III-V My, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-VM „, or Si nanowires and inter vening first trenches; removing the Sio layer, forming third trenches; and removing the second mask.

Date

2017

Authors

SK Patil, AP Jacob

Inventors

Suraj Kumar Patil, Ajey P Jacob

Patent_office

US

Patent_number

9754843

Application_number

15205535