Abstract

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the …

Date

2017

Authors

Ajey P Jacob, Ruilong Xie, Min Gyu Sung, Lars Liebmann, Rinus TP Lee, Bill Taylor

Journal

International Journal of High Speed Electronics and Systems

Volume

26

Issue

01n02

Pages

1740001

Publisher

World Scientific Publishing Company