Abstract

One illustrative method disclosed herein includes, among other things, forming a first episemiconductor material in a Source/drain region of a transistor device, the first episemi conductor material having a first lateral width at an upper Surface thereof, forming a second episemiconductor material on the first episemiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second episemiconductor material has a second lateral width at an upper Surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper Surface of the second episemi conductor material.

Date

2016

Authors

R Xie, WJ Taylor Jr, AP Jacob

Inventors

Ruilong Xie, William J Taylor Jr, Ajey Poovannummoottil Jacob

Patent_office

US

Patent_number

9318552

Application_number

14283404