Abstract

Approaches for isolating source and drain regions in an inte grated circuit (IC) device (eg, a fin field effect transistor (finFET)) are provided. Specifically, the FinPET device com prises a gate structure formed over a finned Substrate; an isolation oxide beneath an active fin channel of the gate struc ture; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Sili con Germanium (SiGe) for a p-channel metal-oxide-semi conductor field-effect transistor (PMOSFET) and N++ Sili con Nitride (SiN) for a n-channel …

Date

2016

Authors

AP Jacob, MK Akarvardar

Inventors

Ajey Poovannummoottil Jacob, Murat K Akarvardar

Patent_office

US

Patent_number

9293587

Application_number

13948374