Abstract

Appl. No.: 14/341,423 A method of forming a FinFET device having Si or high Ge (22) Filed: Jul. 25, 2014 concentration SiGe fins with a narrow width under the gate and a wider width under the spacer and the resulting device Publication Classification are provided. Embodiments include forming fins; forming a dummy gate, with a dummy Oxide thereunder and a nitride (51) Int. Cl. HM on top, on the fins, the dummy gate formed perpendicular HOIL 27/088(2006.01) to the fins; forming a nitride spacer on each side of the dummy HOIL 29/6(2006.01) gate; forming an oxide in-between adjacent gates and pla HOIL 29/66(2006.01) narizing; removing the nitride HM and dummy gate, forming HOIL 21/02(2006.01) a channel between the nitride spacers; oxidizing the fins in the HOIL 2/8234(2006.01) channel; removing the dummy oxide and oxidized portions of HOIL 29/6(2006.01) the fins; and forming a RMG on the fins …

Date

2016

Authors

MK Akarvardar, AP Jacob, A Knorr

Inventors

Murat Kerem Akarvardar, Ajey P Jacob, Andreas Knorr

Patent_office

US

Application_number

14341423