Abstract

BACKGROUND
As the critical dimensions of integrated circuits continue to shrink, a common difficulty faced by both planar and non planar transistor structures is source-to-drain leakage. Typi cally, halo or punchthrough implants are used as counter doped regions under or proximate the channel region to minimize source-to-drain leakage. However, formation of Such implants often causes undesirable doping of, or other damage to, the channel region. Further, these implants are frequently not sufficient to inhibit source-to-drain leakage. A process for inhibiting source-to-drain leakage in planar transistor structures is the use of “silicon-on-nothing or “SON” technology to form an insulator under the gate. Here tofore, such a process has not been effectively utilized for non-planar multigate field effect transistor devices, referred to herein generally as FinFETS. The planar SON process forms a void under the transistor …

Date

April 14, 2015

Authors

MK Akarvardar, AP Jacob

Inventors

Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob

Patent_office

US

Patent_number

9006077

Application_number

13971937