Abstract

Semiconductor structures and fabrication methods are pro vided integrating different fin device architectures on a com mon wafer, for instance, within a common functional device area of the wafer. The method includes: facilitating fabricat ing multiple fin device architectures within a common func tional device wafer area by: providing a wafer with at least one findisposed overa Substrate, the fin including an isolation layer; modifying the fin (s) in a first region of the fin?(s), while protecting the fin in a second region of the fin (s); and pro ceeding with forming one or more fin devices of a first archi tectural type in the first region and one or more fin devices of a second architectural type in the second region. The first architectural type and the second architectural type are dif ferent fin device architectures, such as different fin device isolation architectures, different fin type transistor architec tures, or different fin-type devices or …

Date

2015

Authors

AP Jacob, MK Akarvardar, MJ Hargrove

Inventors

Ajey P Jacob, Murat Kerem Akarvardar, Michael John Hargrove

Patent_office

US

Application_number

13945379