Abstract

Modern integrated circuits (ICs) are designed as massively parallel systems as a consequence of diminishing silicon feature sizes. This has adversely impacted reliability because of increased errors due to process and environmental variations, and particle hits. Viewing hardware errors as analogous to measurement or system noise allows us to borrow results from estimation theory and extend Moore's law. The estimation-theoretic framework provides a design optimization formalization that enables power/reliability trade-off in broad classes of applications. Two applications described here show that specific instantiations of the framework yield significant power savings and system reliability.

Date

March 31, 2008

Authors

Sriram Narayanan, Girish V Varatkar, Douglas L Jones, Naresh R Shanbhag

Conference

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

Pages

1421-1424

Publisher

IEEE