Abstract

A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.

Date

2011

Authors

MC French, L Wang, D Agarwal, A Davoodi

Inventors

Matthew C French, Li Wang, Deepak Agarwal, Azadeh Davoodi

Patent_office

US

Patent_number

8010931

Application_number

11678994