Abstract

I. INTRODUCTION Field Programmable Gate Arrays (FPGAs) have become increasingly popular in high-speed front-end digital signal processing (DSP) applications. Many of the recent advances in FPGA device technology have directly impacted DSP performance, most notably with the inclusion of dedicated multiplier resources. With the availability of more multipliers with better precision, increasingly more sophisticated DSP kernels such as Finite Impulse Response (FIR) filters have grown from a few taps implemented using Lookup-Table (LUT)-based CORDICs [1] to hundreds of taps utilizing embedded multipliers. This particularly benefits twodimensional filters such as those used in image processing, which are bound by multiplier performance [2, 3]. While Moore’s Law has provided more DSP processing power for an FPGA, there is a tradeoff of in power consumption. Dynamic power consumption is described as:

Date

2004

Authors

Matthew French

Journal

Washington, DC, USA