Abstract

Provided is a memory circuit including a pair of cross-coupled inverters, the pair of cross-coupled inverters accessible by bit lines, wherein the access of the bit lines to the pair of cross-coupled inverters is controlled by access transistors, the access transistors controlled by a word line, and a dynamic node between one of the access transistors and one of the bit lines, the dynamic node storing a bit value.

Date

February 12, 2026

Authors

AP Jacob, A Jaiswal, SS Vijayakumar, Z Yin

Inventors

Ajey Poovannummoottil Jacob, Akhilesh Jaiswal, Shwetha Sajitha Vijayakumar, Zihan Yin

Patent_office

US

Application_number

19298098