Publications

Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region

Abstract

One method of forming epi Semiconductor cladding mate rials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement episemiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replace ment gate structure within the replacement gate cavity around the at least one replacement epi Semiconductor cladding material.

Date
2016
Authors
AP Jacob, WP Maszara, JA FRONHEISER
Inventors
Ajey Poovannummoottil Jacob, Witold P Maszara, Jody A FRONHEISER
Patent_office
US
Patent_number
9508853
Application_number
15073936