Publications

Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device

Abstract

One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in posi tion, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor Substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop materialso as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially fill ing the channel cavity with a stressed material.

Date
2016
Authors
X Cai, R Xie, K Cheng, A Khakifirooz, AP Jacob, WP Maszara
Inventors
Xiuyu Cai, Ruilong Xie, Kangguo Cheng, Ali Khakifirooz, Ajey P Jacob, Witold P Maszara
Patent_office
US
Patent_number
9412822
Application_number
14200737