Abstract

One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first episemiconductor material and a second episemiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the Source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to forman epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Date

2016

Authors

AP Jacob, N Loubet

Inventors

Ajey Poovannummoottil Jacob, Nicolas Loubet

Patent_office

US

Patent_number

9263580

Application_number

14223373