Abstract

Decoupled Instruction Stream Computer). The HiDISC provides high performance for loop-based scientific and signal processing programs by exploiting instruction-level parallelism and improving memory system performance by providing decoupled prefetching. In this paper, we present the HiDISC architecture, a sample program to show how the architecture works, and simulation results for five Livermore Loops, discrete convolution, and one other benchmark. The simulation results show a speedup of two to three for HiDISC compared to a uniprocessor with prefetching. The performance advantage of the HiDISC architecture increases as the miss penalty gets larger relative to processor cycles, making it an attractive architecture as the difference between processor speed and DRAM speed continues to grow exponentially.

Date

January 1, 1970

Authors

Stephen P Crago, Alvin Despain, Jean-Luc Gaudiot, Manil Makhija, Wonwoo Ro, Apoorv Srivastava

Journal

Proceedings of MEDEA Workshop