Abstract

Heterogeneous configurable computing systems containing general-purpose processors, special-purpose processors, field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) present several programming and development challenges. The ADAPTERS effort is addressing these challenges by focusing on three technology areas: (1) a unified data flow programming environment, (2) hardware/software partitioning and mapping tool, along with a system level modeling tool, and (3) a dynamic reconfiguration run-time environment for FPGAs. To investigate automatic mapping techniques, a constant false alarm rate (CFAR) application has been implemented on a combined PC/WILDFORCE platform. The combined platform containing FPGAs provided a 20% improvement in the end-to-end latency compared to a software solution running on a PC. An image compression example has …

Date

March 25, 2000

Authors

S Kumar, D Bhatt, S Vestal, B Wren, J Shackleton, H Shirley, R Bhatt, J Golusky, M Vojta, C Nanavati, P Zumsteg, P Symosek, S Crago, B Schott, R Parker, G Gardner

Conference

2000 IEEE Aerospace Conference. Proceedings (Cat. No. 00TH8484)

Volume

5

Pages

487-497

Publisher

IEEE