Abstract

This dissertation presents a novel, high-performance decoupled architecture called HiDISC (Hierarchical Decoupled Instruction Stream Computer). By using three instruction streams, HiDISC exploits instruction-level parallelism and improves memory system performance to provide high-performance execution of loop-based scientific programs. A cost model is presented that shows the cost in silicon area of HiDISC is between 13% and 35% more than a superscalar processor. A variant of the HiDISC architecture that has a superscalar core, the CAPP (Computation and Prefetch Processor), is also presented and has similar latency-tolerance to the HiDISC. The HiDISC has better performance than modern superscalar processors and previously proposed decoupled architectures. Simulation results show that the HiDISC architecture provides a speedup of up to six over an in-order-issue superscalar processor with …

Date

January 23, 1997

Authors

Stephen Philip Crago

Institution

University of Southern California