Abstract

Decoupled Instruction Stream Computer). The HiDISC provides high performance by exploiting instruction-level parallelism and improving memory system performance. In this paper, we present the HiDISC architecture, a sample program to show how the architecture works, and simulation results for two simple, hand-compiled benchmarks. The simulation results show a reduction compared to uniprocessor (without prefetching) and two-level decoupled architectures in the miss rate of several orders of magnitude for one benchmark and several times for another. The reductions in miss rates result in execution time improvements of 31% to 74% for miss penalties ranging from 100 to 250 processor cycles when compared with a 2-level decoupled architecture. The performance advantage of the HiDISC architecture increases as the miss penalty gets larger relative to processor cycles, making it an attractive architecture as the difference between processor speed and DRAM speed continues to grow exponentially.

Date

June 14, 1996

Authors

Stephen P Crago, Apoorv Srivastava, Kevin Obenland, Alvin M Despain