Dr. Lifu Chang joined USC/ISI as Director of The MOSIS Service. He envisions The MOSIS Service as the semiconductor manufacturing and yield enablement provider for advanced chip designs. He will lead The MOSIS Service to achieve effective and successful design-to-yield cycles, between the broad semiconductor research and product communities and the best-in-class foundries. He will ensure the team provides comprehensive service to designers, so that they can deliver design data to fabs with optimized yield qualities and the best manufacturing cycle times. He will also lead The MOSIS Service to perform research activities to advance semiconductor design and process technology co-optimization with USC and other research organizations.

Prior to joining ISI, Dr. Chang has had more than 20 years of work experience in semiconductor device, process technology, Electronic Design Automation (EDA), design enablement, and Design for Manufacturability (DFM) areas. He has held engineering and management positions in companies across EDA, foundry, and fabless design companies. He pioneered DFM technology when he worked as R&D Manager at Clear Shape Technologies. His work resulted in patents that laid critical foundations of multiple DFM EDA tool flows in use worldwide today. He then joined Semiconductor Manufacturing International Corporation, “SMIC” as the Director of Technology Based Design Enablement. At SMIC, he built and led teams of DFM, TCAD, Design Rule, Reliability, Technology IP, etc. to achieve yield enhancement in state-of-the-art design enablement environments. Dr. Chang then joined Qualcomm as the Director of Engineering. He led the DFM Team to achieve high yield for products including Mobile Application Processor SOC, Modem, RF wireless transceiver, Power Management IC, etc. He led the entire company to learn and collaborate with foundries in DFM throughout the product and technology development cycles. He initiated and led development of new DFM flows such as foundry plan-on-record fills for minimizing metal density gradients, custom fill for device performance yield optimization, via redundancy for IR drop and power supply integrity, and OPC pattern analysis and characterization in 7nm process and beyond. He also worked as the DFM Expert at Hisilicon Technologies after Qualcomm. He developed DFM flows and rules for the most advanced Extreme Ultraviolet lithography and the 3DIC processes.

Dr. Chang obtained his Ph.D. degree from Purdue University in 1996, in the area of solid state electronics. He has published nearly 50 journal and conference papers and holds multiple US patents. He received the Elected Membership Award from American Association for the Advancement of Science in 2001. He is a Senior Member of IEEE. He serves in SPIE, The International Society for Optics and Photonics, as committee member for the Design and Process Technology Co-Optimization Program.