Scientists at the University of Southern California Information Sciences Institute (USC ISI) and the University of Wisconsin–Madison have developed the world’s first regenerative photonic memory on a commercial foundry platform, a major step toward practical light-based computing.

The breakthrough addresses a critical bottleneck in modern computing known as “interconnect delay.” As demand for processing power has surged, traditional electronic systems have hit fundamental limits. Metal wires can only transmit electrical signals so fast, suffer from resistance and heat, constraining both speed and efficiency. Meanwhile, the hardware required to meet growing computational needs continues to expand in size and energy consumption.

As computing demands continue to climb, modern electronic systems face several well known limitations, including interconnect delay, heat, wiring limits, an equally pressing barrier is the speed and energy required to store and retrieve  data. Even photonic processors, which can move information using light at extremely high speeds, are constrained by the need to store data in traditional electronic memory. This constant switching between optical and electrical domains wastes energy and limits system performance.

Photonic, or light-based, computing offers a promising path to faster and more energy-efficient systems by transmitting data with minimal electrical resistance or heat. But to build a complete photonic computer, researchers need a memory technology that also operates in the optical domain. Until now, that component has been missing.

This shift promises dramatically faster speeds and greater energy efficiency, offering a path forward where conventional technologies have reached an impasse. However, a major missing piece has been a robust, scalable memory system that operates in the optical domain.

The first “regenerative” photonic latch

To solve this issue, the research team has achieved an experimental first: a “regenerative” photonic latch, the optical counterpart to an electronic memory bit, built on a commercial silicon photonics platform. This represents more than a laboratory proof-of-concept; it’s a functional component manufactured using industry-standard processes.

Building on this success, the researchers have already published simulation studies exploring how their photonic latch architecture could scale into a complete photonic SRAM system, the optical counterpart to the SRAM that underpins today’s electronic processors. Such memory would be the optical equivalent of the SRAM used in today’s electronic processors, potentially bringing light-based computing closer to real-world applications.

The new device, developed by the team led by ISI’s Director of Advanced Electronics Ajey P. Jacob (USC ISI) and professor Akhilesh R. Jaiswal (UW-Madison), solves this by creating a memory cell that can store data as light and, crucially, “regenerate” the signal to keep it stable against noise; just like standard electronic RAM, but faster.

“To fully realize the potential of photonic computing for AI accelerators and tensor cores, we need photonic memory that is just as versatile and robust as its electrical counterparts,” said Jacob. “Our Photonic Latch demonstrates that we can build these essential building blocks using standard, mass-producible manufacturing processes.”

Ready to Go Commercial Scalability via Global Foundries 

Unlike previous experimental photonic memories that required exotic materials or extreme power, this new device was fabricated on the GlobalFoundries Fotonix™ platform. This is a commercial 300mm monolithic silicon photonics platform, meaning the technology is ready to scale today, rather than being limited to laboratory experiments.

“This work represents a key milestone toward integrated photonic in-memory computing,” said Jaiswal of UW-Madison. “By demonstrating a cross-coupled differential regenerative architecture, we have shown that it is possible to build scalable, energy-efficient optical memory arrays that can interface directly with future photonic processors.”

The work will be presented at the 2025 IEEE International Electron Devices Meeting (IEDM), the world’s premier forum for reporting technological breakthroughs in semiconductor and electronic device technology, held from December 6–10 in San Francisco.

The paper, titled “Demonstration of a Cross-Coupled Differential Regenerative Photonic Latch for Integrated Ultra-fast On-Chip Memory,” will be part of  the IEDM 2025 technical sessions. The authors include Md Abdullah-Al Kaiser and Sugeet Sunder (Equal Contributors), alongside PIs Jaiswal and Jacob.

This research was supported by the Defense Advanced Research Projects Agency (DARPA) and the PM Mukund Vengalattore under Grant N660012424003. 

Published on December 4th, 2025

Last updated on December 4th, 2025