Publications
This section contains publications published by ISI over the past several decades.
2016
FinFET device including a uniform silicon alloy fin
AP Jacob, JA Fronheiser, MK Akarvardar, S Bentley
US Patent 9,406,803, 2016
Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
MK Akarvardar, AP Jacob
US Patent 9,385,233, 2016
Semiconductor devices with conductive contact structures having a larger metal silicide contact area
R Xie, WJ Taylor Jr, AP Jacob
US Patent App. 15/065,998, 2016
Methods of forming a non-planar ultra-thin body semiconductor device and the resulting devices
AP Jacob, R Xie, M Hargrove
US Patent 9,373,721, 2016
FINFET technology featuring high mobility SiGe channel for 10nm and beyond
Dechao Guo, G Karve, G Tsutsui, Kwan-Yong Lim, R Robison, T Hook, R Vega, Derrick Liu, S Bedell, Shogo Mochizuki, F Lie, Kerem Akarvardar, Miaomiao Wang, Ruqiang Bao, Sean Burns, Victor Chan, Kangguo Cheng, J Demarest, Jody Fronheiser, Pouya Hashemi, James Kelly, Juntao Li, Nicolas Loubet, Pietro Montanini, Bhagawan Sahu, M Sankarapandian, Stuart Sieg, J Sporre, J Strane, R Southwick, N Tripathi, Rajasekhar Venigalla, Jing Wang, K Watanabe, Chun-Wing Yeung, Dinesh Gupta, Bruce Doris, Nelson Felix, Ajey Jacob, H Jagannathan, Sivananda Kanakasabapathy, Renee Mo, Vijay Narayanan, Devendra Sadana, Phil Oldiges, James Stathis, Tenko Yamashita, Vamsi Paruchuri, Matthew Colburn, Andreas Knorr, Rama Divakaruni, Huiming Bu, M Khare
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Transistors comprising doped region-gap-doped region structures and methods of fabrication
SJ Bentley, AP Jacob, CY Chen, T Yamashita
US Patent 9,368,591, 2016
Methods of forming substrates comprised of different semiconductor materials and the resulting device
BJ Pawlak, S Bentley, A Jacob
US Patent 9,368,578, 2016
Channel cladding last process flow for forming a channel region on a FinFET device
AP Jacob, WP Maszara, JA Fronheiser
US Patent 9,362,405, 2016
FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
MH Chi, A Jacob, A Paul
US Patent 9,362,277, 2016
Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
X Cai, R Xie, AP Jacob, WP Maszara, K Cheng, A Khakifirooz
US Patent 9,349,840, 2016
Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material
AP Jacob, B Doris, K Cheng, A Khakifirooz, K Rim
US Patent 9,349,658, 2016
Fin transformation process and isolation structures facilitating different Fin isolation schemes
AP Jacob, K Cheng, BB Doris, N Loubet, P Khare, R Divakaruni
US Patent 9,349,730, 2016
Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region
AP Jacob, M Hargrove, JA Fronheiser, MK Akarvardar
US Patent 9,343,300, 2016
Self-aligned dual-height isolation for bulk FinFET
MK Akarvardar, SJ Bentley, K Cheng, BB Doris, J Fronheiser, AP Jacob, ...
US Patent 9,324,790, 2016
Methods of removing fins for finfet semiconductor devices
R Xie, A Knorr, AP Jacob, M Hargrove
US Patent 9,318,342, 2016
Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
R Xie, WJ Taylor Jr, AP Jacob
US Patent 9,318,552, 2016
Methods of forming FinFET devices with alternative channel materials
AP Jacob, MK Akarvardar, M Hargrove, R Xie
US Patent 9,312,387, 2016
Device isolation in FinFET CMOS
AP Jacob, MK Akarvardar, S Bentley, T Nagumo, K Cheng, BB Doris, ...
US Patent 9,305,846, 2016
Finfet semiconductor device with isolated channel regions
AP Jacob, N Loubet
US Patent App. 14/963,683, 2016
Semiconductor devices with replacement gate structures
R Xie, X Cai, AC Wei, Q Zhang, AP Jacob, M Hargrove
US Patent App. 14/963,378, 2016